/*
 * sound\soc\sunxi\audiocodec\sun8iw8_sndcodec.h
 * (C) Copyright 2010-2016
 * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
 * liushaohua <liushaohua@allwinnertech.com>
 *
 * some simple description for this code
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 */
#ifndef _SUN8IW8_CODEC_H
#define _SUN8IW8_CODEC_H
#include <mach/platform.h>
/*Codec Register*/
#define baseaddr		SUNXI_AUDIO_VBASE
#define CODEC_BASSADDRESS		(0x01c22c00)
#define SUNXI_DAC_DPC		(0x00)
#define SUNXI_DAC_FIFOC		(0x04)
#define SUNXI_DAC_FIFOS		(0x08)

#define SUNXI_ADC_FIFOC		(0x10)
#define SUNXI_ADC_FIFOS		(0x14)
#define SUNXI_ADC_RXDATA		(0x18)
#define SUNXI_DAC_TXDATA		(0x20)

#define SUNXI_DAC_CNT			 (0x40)
#define SUNXI_ADC_CNT			 (0x44)
#define SUNXI_DAC_DEBUG			(0x48)
#define SUNXI_ADC_DEBUG			(0x4c)
#define SUNXI_DAC_DAP_CTR		(0X60)
#define SUNXI_ADC_DAP_CTR		(0X70)
#define SUNXI_ADC_DAP_LCTR		(0X74)
#define	SUNXI_ADC_DAP_RCTR		(0X78)
#define SUNXI_ADC_DAP_PARA		(0X7C)
#define SUNXI_ADC_DAP_LAC		(0X80)
#define SUNXI_ADC_DAP_LDAT		(0X84)
#define SUNXI_ADC_DAP_RAC		(0X88)
#define SUNXI_ADC_DAP_RDAT		(0X8C)
#define SUNXI_ADC_DAP_HPFC		(0X90)
#define SUNXI_ADC_DAP_LINAC		(0X94)
#define SUNXI_ADC_DAP_RNAC		(0X98)
#define SUNXI_ADC_DAP_OPT		(0X9C)
#define SUNXI_DAC_DRC_HHPFC		(0X100)
#define SUNXI_DAC_DRC_LHPFC		(0X104)
#define SUNXI_DAC_DRC_CTRL		(0X108)
#define SUNXI_DAC_DRC_LPFHAT		(0X10C)
#define SUNXI_DAC_DRC_LPFLAT		(0X110)
#define SUNXI_DAC_DRC_RPFHAT		(0X114)
#define SUNXI_DAC_DRC_RPFLAT		(0X118)
#define SUNXI_DAC_DRC_LPFHRT		(0X11C)
#define SUNXI_DAC_DRC_LPFLRT		(0X120)
#define SUNXI_DAC_DRC_RPFHRT		(0X124)
#define SUNXI_DAC_DRC_RPFLRT		(0X128)
#define SUNXI_DAC_DRC_LRMSHAT		(0X12C)
#define SUNXI_DAC_DRC_LRMSLAT		(0X130)
#define SUNXI_DAC_DRC_RRMSHAT		(0X134)
#define SUNXI_DAC_DRC_RRMSLAT		(0X138)
#define SUNXI_DAC_DRC_HCT		(0X13C)
#define SUNXI_DAC_DRC_LCT		(0X140)
#define SUNXI_DAC_DRC_HKC		(0X144)
#define SUNXI_DAC_DRC_LKC		(0X148)
#define SUNXI_DAC_DRC_HOPC		(0X14C)
#define SUNXI_DAC_DRC_LOPC		(0X150)
#define SUNXI_DAC_DRC_HLT		(0X154)
#define SUNXI_DAC_DRC_LLT		(0X158)
#define SUNXI_DAC_DRC_HKI		(0X15C)
#define SUNXI_DAC_DRC_LKI		(0X160)
#define SUNXI_DAC_DRC_HOPL		(0X164)
#define SUNXI_DAC_DRC_LOPL		(0X168)
#define SUNXI_DAC_DRC_HET		(0X16C)
#define	SUNXI_DAC_DRC_LET		(0X170)
#define SUNXI_DAC_DRC_HKE		(0X174)
#define SUNXI_DAC_DRC_LKE		(0X178)
#define SUNXI_DAC_DRC_HOPE		(0X17C)
#define SUNXI_DAC_DRC_LOPE		(0X180)
#define SUNXI_DAC_DRC_HKN		(0X184)
#define SUNXI_DAC_DRC_LKN		(0X188)
#define SUNXI_DAC_DRC_SFHAT		(0X18C)
#define SUNXI_DAC_DRC_SFLAT		(0X190)
#define SUNXI_DAC_DRC_SFHRT		(0X194)
#define	SUNXI_DAC_DRC_SFLRT		(0X198)
#define	SUNXI_DAC_DRC_MXGHS		(0X19C)
#define SUNXI_DAC_DRC_MXGLS		(0X1A0)
#define SUNXI_DAC_DRC_MNGHS		(0X1A4)
#define SUNXI_DAC_DRC_MNGLS		(0X1A8)
#define SUNXI_DAC_DRC_EPSHC		(0X1AC)
#define SUNXI_DAC_DRC_EPSLC		(0X1B0)
#define SUNXI_DAC_DRC_OPT		(0X1B4)
#define SUNXI_DAC_HPF_HG		(0x1B8)
#define SUNXI_DAC_HPF_LG		(0x1BC)


#define SUNXI_ADC_DRC_HHPFC		(0X200)
#define SUNXI_ADC_DRC_LHPFC		(0X204)
#define SUNXI_ADC_DRC_CTRL		(0X208)
#define SUNXI_ADC_DRC_LPFHAT		(0X20C)
#define SUNXI_ADC_DRC_LPFLAT		(0X210)
#define SUNXI_ADC_DRC_RPFHAT		(0X214)
#define SUNXI_ADC_DRC_RPFLAT		(0X218)
#define SUNXI_ADC_DRC_LPFHRT		(0X21C)
#define SUNXI_ADC_DRC_LPFLRT		(0X220)
#define SUNXI_ADC_DRC_RPFHRT		(0X224)
#define SUNXI_ADC_DRC_RPFLRT		(0X228)
#define SUNXI_ADC_DRC_LRMSHAT		(0X22C)
#define SUNXI_ADC_DRC_LRMSLAT		(0X230)
#define SUNXI_ADC_DRC_RRMSHAT		(0X234)
#define SUNXI_ADC_DRC_RRMSLAT		(0X238)
#define SUNXI_ADC_DRC_HCT		(0X23C)
#define SUNXI_ADC_DRC_LCT		(0X240)
#define SUNXI_ADC_DRC_HKC		(0X244)
#define SUNXI_ADC_DRC_LKC		(0X248)
#define SUNXI_ADC_DRC_HOPC		(0X24C)
#define SUNXI_ADC_DRC_LOPC		(0X250)
#define SUNXI_ADC_DRC_HLT		(0X254)
#define SUNXI_ADC_DRC_LLT		(0X258)
#define SUNXI_ADC_DRC_HKI		(0X25C)
#define SUNXI_ADC_DRC_LKI		(0X260)
#define SUNXI_ADC_DRC_HOPL		(0X264)
#define SUNXI_ADC_DRC_LOPL		(0X268)
#define SUNXI_ADC_DRC_HET		(0X26C)
#define SUNXI_ADC_DRC_LET		(0X270)
#define	SUNXI_ADC_DRC_HKE		(0X274)
#define SUNXI_ADC_DRC_LKE		(0X278)
#define SUNXI_ADC_DRC_HOPE		(0X27C)
#define SUNXI_ADC_DRC_LOPE		(0X280)
#define SUNXI_ADC_DRC_HKN		(0X284)
#define SUNXI_ADC_DRC_LKN		(0X288)
#define SUNXI_ADC_DRC_SFHAT		(0X28C)
#define SUNXI_ADC_DRC_SFLAT		(0X290)
#define SUNXI_ADC_DRC_SFHRT		(0X294)
#define SUNXI_ADC_DRC_SFLRT		(0X298)
#define SUNXI_ADC_DRC_MXGHS		(0X29C)
#define SUNXI_ADC_DRC_MXGLS		(0X2A0)
#define SUNXI_ADC_DRC_MNGHS		(0X2A4)
#define SUNXI_ADC_DRC_MNGLS		(0X2A8)
#define SUNXI_ADC_DRC_EPSHC		(0X2AC)
#define SUNXI_ADC_DRC_EPSLC		(0X2B0)
#define SUNXI_ADC_DRC_OPT		(0X2B4)
#define SUNXI_ADC_HPF_HG		(0x2B8)
#define SUNXI_ADC_HPF_LG		(0x2BC)

/*DAC Digital Part Control Register
* codecbase+0x00
*/
#define DAC_EN                    (31)
#define DIGITAL_VOL               (12)

/*DAC FIFO Control Register
* codecbase+0x04
*/
#define DAC_FS                    (29)
#define FIR_VERSION				  (28)
#define LAST_SE                   (26)
#define TX_FIFO_MODE              (24)
#define DRA_LEVEL                 (21)
#define TX_TRI_LEVEL              (8)
#define ADDA_LOOP_EN              (7)
#define DAC_MODE                  (6)
#define TASR                      (5)
#define DAC_DRQ                   (4)
#define DAC_FIFO_FLUSH            (0)

/*ADC FIFO Control Register
* codecbase+0x10
*/
#define ADFS                	  (29)
#define ADC_EN                	  (28)
#define ADC_DIG_MIC_EN			  (27)
#define RX_FIFO_MODE              (24)
#define ADCFDT					  (17)
#define ADCDFEN					  (16)
#define RX_TRI_LEVEL              (8)
#define ADC_MODE                  (7)
#define RASR                      (6)
#define ADC_DRQ                   (4)
#define ADC_FIFO_FLUSH            (0)

/*DAC Debug Register
* codecbase+0x48
*/
#define DAC_MODU_SELECT			  (11)
#define DAC_PATTERN_SELECT		  (9)
#define DAC_SWP					  (6)

#define ADDA_PR_CFG_REG     	  (SUNXI_AUDIO_VBASE+0x400)

#define HP_VOLC					  (0x00)
#define LOMIXSC					  (0x01)
#define ROMIXSC					  (0x02)
#define DAC_PA_SRC				  (0x03)

#define MIC_GCTR			  (0x06)
#define HP_CTRL			  (0x07)
#define LINEOUT_VOLC			  (0x09)

#define MIC2_CTRL		  (0x0A)
#define BIAS_MIC_CTRL		  (0x0B)

#define LADC_MIX_MUTE		  		  (0x0C)
#define RADC_MIX_MUTE				  (0x0D)
#define PA_ANTI_POP_CTRL				  (0x0E)
#define AC_ADC_CTRL				  (0x0F)

#define OPADC_CTRL				  (0x10)
#define OPMIC_CTRL				  (0x11)
#define ZERO_CROSS_CTRL				  (0x12)
#define ADC_FUN_CTRL		                (0x13)
#define CALIBRTAION_CTRL		                (0x14)

/*
*	apb0 base
*	0x00 HP_VOLC
*/
#define HPVOL			(0)

/*
*	apb0 base
*	0x01 LOMIXSC
*/
#define LMIXMUTE				  (0)
#define LMIXMUTEDACR			  (0)
#define LMIXMUTEDACL			  (1)
#define LMIXMUTELINEINL			  (2)
#define LMIXMUTEMIC2BOOST		  (5)
#define LMIXMUTEMIC1BOOST		  (6)

/*
*	apb0 base
*	0x02 ROMIXSC
*/
#define RMIXMUTE				  (0)
#define RMIXMUTEDACL			  (0)
#define RMIXMUTEDACR			  (1)
#define RMIXMUTELINEINR			  (2)
#define RMIXMUTEMIC2BOOST		  (5)
#define RMIXMUTEMIC1BOOST		  (6)

/*
*	apb0 base
*	0x03 DAC_PA_SRC
*/
#define DACAREN			(7)
#define DACALEN			(6)
#define RMIXEN			(5)
#define LMIXEN			(4)
#define RHPPAMUTE		(3)
#define LHPPAMUTE		(2)
#define RHPIS			(1)
#define LHPIS			(0)

/*
*	apb0 base
*	0x06 MICIN_GCTRL
*/
#define MIC1G			(4)
#define MIC2G			(0)

/*
*	apb0 base
*	0x07 PAEN_HP_CTRL
*/
#define HPPAEN			 (7)
#define HPCOM_FC		 (5)
#define COMPTEN			 (4)
#define COS_SLOPE_CTRL		(2)
#define LTRNMUTE		 (1)
#define RTLNMUTE		 (0)

/*
*
*	0x09 LINEOUT_VOLC
*/
#define LINEOUTVOL		 (3)

/*
*	apb0 base
*	0x0A MIC2G_LINEEN_CTRL
*/
#define MIC2AMPEN		 (7)
#define MIC2BOOST		 (4)
#define LINEOUTLEFTEN		 (3)
#define	LINEOUTRIGHTEN		 (2)
#define LEFTLINEOUTSRC		 (1)
#define RIGHTLINEOUTSRC		 (0)

/*
*	apb0 base
*	0x0B MIC1G_MICBIAS_CTRL
*/
#define HMICBIASEN              (7)
#define MMICBIASEN		 (6)
#define MIC2_SS                         (4)
#define MIC1AMPEN		 (3)
#define MIC1BOOST		 (0)

/*
*	apb0 base
*	0x0C LADCMIXSC
*/
#define LADCMIXMUTE		 		  (0)
#define LADCMIXMUTEMIC1BOOST	  (6)
#define LADCMIXMUTEMIC2BOOST	  (5)
#define LADCMIXMUTELINEINL		  (2)
#define LADCMIXMUTELOUTPUT		  (1)
#define LADCMIXMUTEROUTPUT		  (0)

/*
*	apb0 base
*	0x0D RADCMIXSC
*/
#define RADCMIXMUTE		          (0)
#define RADCMIXMUTEMIC1BOOST	  (6)
#define RADCMIXMUTEMIC2BOOST	  (5)
#define RADCMIXMUTELINEINR		  (2)
#define RADCMIXMUTEROUTPUT		  (1)
#define RADCMIXMUTELOUTPUT		  (0)

/*
*	0x0E ADC_AP_EN
*/
#define PA_ANTI_POP_CTL			 (0)

/*
*	apb0 base
*	0x0F ADC_AP_EN
*/
#define ADCREN			 (7)
#define ADCLEN			 (6)
#define ADCG			 (0)

/*
*	apb0 base
*	0x12 ZERO_CROSS_CTRL
*/
#define ZERO_CROSS_EN 	  (7)
#define PA_SLOPE_SELECT	  (3)

#define codec_rdreg(reg)	  readl((baseaddr+(reg)))
#define codec_wrreg(reg,val)  writel((val),(baseaddr+(reg)))

extern int snd_codec_info_volsw(struct snd_kcontrol *kcontrol,
		struct	snd_ctl_elem_info	*uinfo);
extern int snd_codec_get_volsw(struct snd_kcontrol	*kcontrol,
		struct	snd_ctl_elem_value	*ucontrol);
extern int snd_codec_put_volsw(struct	snd_kcontrol	*kcontrol,
	struct	snd_ctl_elem_value	*ucontrol);

/*
* Convenience kcontrol builders
*/
#define CODEC_SINGLE_VALUE(xreg, xshift, xmax,	xinvert)\
		((unsigned long)&(struct codec_mixer_control)\
		{.reg	=	xreg,	.shift	=	xshift,	.rshift	=	xshift,	.max	=	xmax,\
   	.invert	=	xinvert})

#define CODEC_SINGLE(xname,	reg,	shift,	max,	invert)\
{	.iface	= SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,\
	.info	= snd_codec_info_volsw,	.get = snd_codec_get_volsw,\
	.put	= snd_codec_put_volsw,\
	.private_value	= CODEC_SINGLE_VALUE(reg, shift, max, invert)}

/*	mixer control*/
struct	codec_mixer_control{
	int		min;
	int     max;
	int     where;
	unsigned int mask;
	unsigned int reg;
	unsigned int rreg;
	unsigned int shift;
	unsigned int rshift;
	unsigned int invert;
	unsigned int value;
};

#endif
